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1 ltc2602/ltc2612/ltc2622 2602fa , ltc and lt are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. block diagra w descriptio u applicatio s u features v out a ref cs/ld sck v out b gnd v cc sdi 2602 bd01 8 1 2 4 3 5 7 6 16-bit dac a 16-bit dac b decode control logic 24-bit shift register register register register register the ltc 2602/ltc2612/ltc2622 are dual 16-,14- and 12-bit, 2.5v-to-5.5v rail-to-rail voltage-output dacs, in a tiny 8-lead msop package. they have built-in high per- formance output buffers and are guaranteed monotonic. these parts establish advanced performance standards for output drive, crosstalk and load regulation in single- supply, voltage output multiples. the parts use a simple spi/microwire compatible 3-wire serial interface which can be operated at clock rates up to 50mhz. the ltc2602/ltc2612/ltc2622 incorporate a power- on reset circuit. during power-up, the voltage outputs rise less than 10mv above zero scale, and after power- up, they stay at zero scale until a valid write and update take place. smallest pin-compatible dual dacs: ltc2602: 16-bits ltc2612: 14-bits ltc2622: 12-bits guaranteed 16-bit monotonic over temperature wide 2.5v to 5.5v supply range low power operation: 300 a per dac at 3v individual channel power-down to 1 a, max ultralow crosstalk between dacs (30 v) high rail-to-rail output drive ( 15ma) double-buffered data latches pin-compatible 10-bit version (ltc1661) tiny 8-lead msop package mobile communications process control and industrial automation instrumentation automatic test equipment differential nonlinearity (dnl)(ltc2602) code 0 16384 32768 49152 65535 error (lsb) 2602 ta01 1.0 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 v cc = 5v v ref = 4.096v ltc2602 dual 16-/14-/12-bit rail-to-rail dacs in 8-lead msop
2 ltc2602/ltc2612/ltc2622 2602fa a u g w a w u w a r b s o lu t exi t i s order part number wu u package / o rder i for atio (note 1) any pin to gnd ........................................... 0.3v to 6v any pin to v cc ........................................................ ?v to 0.3v maximum junction temperature ......................... 125 c operating temperature range ltc2602c/ltc2612c/ltc2622c .......... 0 c to 70 c ltc2602i/ltc2612i/ltc2622i .......... 40 c to 85 c storage temperature range ................ 65 c to 150 c lead temperature (soldering, 10 sec)................ 300 c ms8 part marking e lectr ic al c c hara terist ics ltc2602cms8 ltc2602ims8 ltc2612cms8 ltc2612ims8 ltc2622cms8 ltc2622ims8 ltacx ltacy ltacz ltada ltadb ltadc the denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 2.5v to 5.5v, v ref v cc , v out unloaded, unless otherwise noted. ltc2622 ltc2612 ltc2602 symbol parameter conditions min typ max min typ max min typ max units dc performance resolution 12 14 16 bits monotonicity v cc = 5v, v ref = 4.096v (note 2) 12 14 16 bits dnl differential nonlinearity v cc = 5v, v ref = 4.096v (note 2) 0.5 1 1lsb inl integral nonlinearity v cc = 5v, v ref = 4.096v (note 2) 0.75 4 3 16 12 64 lsb load regulation v ref = v cc = 5v, midscale i out = 0ma to 15ma sourcing 0.025 0.125 0.1 0.5 0.4 2 lsb/ma i out = 0ma to 15ma sinking 0.05 0.125 0.2 0.5 0.65 2 lsb/ma v ref = v cc = 2.5v, midscale i out = 0ma to 7.5ma sourcing 0.05 0.25 0.2 1 0.9 4 lsb/ma i out = 0ma to 7.5ma sinking 0.1 0.25 0.4 1 1.3 4 lsb/ma zse zero-scale error v cc = 5v, v ref = 4.096v code = 0 19 19 19 mv v os offset error v cc = 5v, v ref = 4.096v (note 7) 1 9 1 9 1 9mv v os temperature 5 5 5 v/ c coefficient ge gain error v cc = 5v, v ref = 4.096v 0.1 0.7 0.1 0.7 0.1 0.7 %fsr gain temperature 3 3 3 ppm/ c coefficient t jmax = 125 c, ja = 300 c/w 1 2 3 4 cs/ld sck sdi ref 8 7 6 5 v out a gnd v cc v out b top view ms8 package 8-lead plastic msop order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ consult ltc marketing for parts specified with wider operating temperature ranges.
3 ltc2602/ltc2612/ltc2622 2602fa e lectr ic al c c hara terist ics the denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 2.5v to 5.5v, v ref v cc , v out unloaded, unless otherwise noted. ltc2602/ltc2612/ltc2622 symbol parameter conditions min typ max units psrr power supply rejection ratio v cc = 5v 10% 80 db r out dc output impedance v ref = v cc = 5v, midscale; 15ma i out 15ma 0.05 0.15 ? v ref = v cc = 2.5v, midscale; 7.5ma i out 7.5ma 0.05 0.15 ? dc crosstalk (note 4) due to full scale output change (note 5) 30 v due to load current change 16 v/ma due to powering down (per channel) 4 v i sc short-circuit output current v cc = 5.5v, v ref = 5.5v code: zero scale; forcing output to v cc 15 34 60 ma code: full scale; forcing output to gnd 15 38 60 ma v cc = 2.5v, v ref = 2.5v code: zero scale; forcing output to v cc 7.5 20 50 ma code: full scale; forcing output to gnd 7.5 28 50 ma reference input input voltage range 0v cc v resistance normal mode 44 64 80 k ? capacitance 23 pf i ref reference current, power down mode all dacs powered down 0.001 1 a power supply v cc positive supply voltage for specified performance 2.5 5.5 v i cc supply current v cc = 5v (note 3) 0.7 1.3 ma v cc = 3v (note 3) 0.6 1 ma all dacs powered down (note 3) v cc = 5v 0.35 1 a all dacs powered down (note 3) v cc = 3v 0.10 1 a digital i/o v ih digital input high voltage v cc = 2.5v to 5.5v 2.4 v v cc = 2.5v to 3.6v 2.0 v v il digital input low voltage v cc = 4.5v to 5.5v 0.8 v v cc = 2.7v to 5.5v 0.6 v v cc = 2.5v to 5.5v 0.5 v i lk digital input leakage v in = gnd to v cc 1 a c in digital input capacitance (note 6) 8pf ltc2622 ltc2612 ltc2602 symbol parameter conditions min typ max min typ max min typ max units ac performance t s settling time (note 8) 0.024% ( 1lsb at 12 bits) 7 7 7 s 0.006% ( 1lsb at 14 bits) 9 9 s 0.0015% ( 1lsb at 16 bits) 10 s settling time for 0.024% ( 1lsb at 12 bits) 2.7 2.7 2.7 s 1lsb step (note 9) 0.006% ( 1lsb at 14 bits) 4.8 4.8 s 0.0015% ( 1lsb at 16 bits) 5.2 s voltage output slew rate 0.80 0.80 0.80 v/ s capacitive load driving 1000 1000 1000 pf glitch impulse at midscale transition 12 12 12 nv ?s multiplying bandwidth 180 180 180 khz e n output voltage noise at f = 1khz 120 120 120 nv/ hz density at f = 10khz 100 100 100 nv/ hz output voltage noise 0.1hz to 10hz 15 15 15 v p-p
4 ltc2602/ltc2612/ltc2622 2602fa typical perfor a ce characteristics uw (ltc2602) integral nonlinearity (inl) differential nonlinearity (dnl) inl vs temperature code 0 16384 32768 49152 65535 inl (lsb) 2602 g20 32 24 16 8 0 ? ?6 ?4 ?2 v cc = 5v v ref = 4.096v code 0 16384 32768 49152 65535 dnl (lsb) 2602 g21 1.0 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 v cc = 5v v ref = 4.096v temperature ( c) ?0 ?0 ?0 10 30 50 70 90 inl (lsb) 2602 g22 32 24 16 8 0 ? ?6 ?4 ?2 v cc = 5v v ref = 4.096v inl (pos) inl (neg) ti i g characteristics u w the denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (see figure 1) (note 6) note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: linearity and monotonicity are defined from code k l to code 2 n ?1, where n is the resolution and k l is given by k l = 0.016(2 n /v ref ), rounded to the nearest whole code. for v ref = 4.096v and n = 16, k l = 256 and linearity is defined from code 256 to code 65,535. note 3: digital inputs at 0v or v cc . note 4: dc crosstalk is measured with v cc = 5v and v ref = 4.096v, with the measured dac at midscale, unless otherwise noted. note 5: r l = 2k ? to gnd or v cc at the output of the dac not being tested. note 6: guaranteed by design and not production tested. note 7: inferred from measurement at code 256 (ltc2602), code 64 (ltc2612) or code 16 (ltc2622), and at fullscale. note 8: v cc = 5v, v ref = 4.096v. dac is stepped 1/4 scale to 3/4 scale and 3/4 scate to 1/4 scale. load is 2k in parallel with 200pf to gnd. note 9: v cc = 5v, v ref = 4.096v. dac is stepped lbs between half scale and half scale ?. load is 2k in parallel with 200pf to gnd. ltc2602/ltc2612/ltc2622 symbol parameter conditions min typ max units v cc = 2.5v to 5.5v t 1 sdi valid to sck setup 4ns t 2 sdi valid to sck hold 4ns t 3 sck high time 9ns t 4 sck low time 9ns t 5 cs/ld pulse width 10 ns t 6 lsb sck high to cs/ld high 7ns t 7 cs/ld low to sck high 7ns t 10 cs/ld high to sck positive edge 7ns sck frequency 50% duty cycle 50 mhz
5 ltc2602/ltc2612/ltc2622 2602fa integral nonlinearity (inl) code 0 4096 8192 12288 16383 inl (lsb) 2602 g28 8 6 4 2 0 ? ? ? ? v cc = 5v v ref = 4.096v (ltc2602) typical perfor a ce characteristics uw dnl vs temperature inl vs v ref dnl vs v ref settling to 1lsb settling of full-scale step temperature ( c) ?0 ?0 ?0 10 30 50 70 90 dnl (lsb) 2602 g23 1.0 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 v cc = 5v v ref = 4.096v dnl (pos) dnl (neg) v ref (v) 0 1 2 3 4 5 inl (lsb) 2602 g24 32 24 16 8 0 ? ?6 ?4 ?2 v cc = 5.5v inl (pos) inl (neg) v ref (v) 0 1 2 3 4 5 dnl (lsb) 2602 g25 1.5 1.0 0.5 0 0.5 1.0 1.5 v cc = 5.5v dnl (pos) dnl (neg) 2 s/div 2602 g26 v out 100 v/div cs/ld 2v/div v cc = 5v, v ref = 4.096v 1/4-scale to 3/4-scale step r l = 2k, c l = 200pf average of 2048 events 9.7 s 5 s/div 2602 g27 v out 100 v/div cs/ld 2v/div v cc = 5v, v ref = 4.096v code 512 to 65535 step average of 2048 events settling to 1lsb 12.3 s (ltc2612) differential nonlinearity (dnl) settling to 1lsb code 0 4096 8192 12288 16383 dnl (lsb) 2602 g29 1.0 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 v cc = 5v v ref = 4.096v 2 s/div 2602 g30 v out 100 v/div cs/ld 2v/div v cc = 5v, v ref = 4.096v 1/4-scale to 3/4-scale step r l = 2k, c l = 200pf average of 2048 events 8.9 s
6 ltc2602/ltc2612/ltc2622 2602fa (ltc2622) integral nonlinearity (inl) differential nonlinearity (dnl) settling to 1lsb code 0 1024 2048 3072 4095 inl (lsb) 2602 g31 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 v cc = 5v v ref = 4.096v code 0 1024 2048 3072 4095 dnl (lsb) 2602 g32 v cc = 5v v ref = 4.096v 1.0 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 2 s/div 2602 g33 v out 1mv/div cs/ld 2v/div v cc = 5v, v ref = 4.096v 1/4-scale to 3/4-scale step r l = 2k, c l = 200pf average of 2048 events 6.8 s typical perfor a ce characteristics uw (ltc2602/ltc2612/ltc2622) current limiting load regulation offset error vs temperature i out (ma) ?0 ?0 ?0 ?0 0 10 20 30 40 ? v out (v) 2602 g01 0.10 0.08 0.06 0.04 0.02 0 0.02 0.04 0.06 0.08 0.10 v ref = v cc = 5v v ref = v cc = 3v v ref = v cc = 5v v ref = v cc = 3v code = midscale i out (ma) 35 25 15 5 5 15 25 35 ? v out (mv) 2602 g02 1.0 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 v ref = v cc = 5v code = midscale v ref = v cc = 3v temperature ( c) ?0 ?0 ?0 10 30 50 70 90 offset error (mv) 2602 g03 3 2 1 0 ? ? ? gain error vs temperature offset error vs v cc zero-scale error vs temperature temperature ( c) ?0 ?0 ?0 10 30 50 70 90 zero-scale error (mv) 2602 g04 3 2.5 2.0 1.5 1.0 0.5 0 temperature ( c) ?0 ?0 ?0 10 30 50 70 90 gain error (%fsr) 2602 g05 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 v cc (v) 2.5 3 3.5 4 4.5 5 5.5 offset error (mv) 2602 g06 3 2 1 0 ? ? ?
7 ltc2602/ltc2612/ltc2622 2602fa 2.5 s/div v out 0.5v/div cs/ld 5v/div 2602 g14 v cc = 5v v ref = 2v one dac in power down mode v out 10mv/div 250 s/div 2602 g11 v cc 1v/div 4mv peak 4mv peak v out 10mv/div cs/ld 5v/div 2.5 s/div 2602 g10 12nv-s typ logic voltage (v) 0 0.2 i cc (ma) 0.4 0.8 1.0 1.2 1.6 0.5 2.5 3.5 2602 g13 0.6 1.4 2 4.5 5 1 1.5 34 v cc = 5v sweep sck, sdi and cs/ld 0v to v cc v cc (v) 2.5 3 3.5 4 4.5 5 5.5 i cc (na) 2602 g08 450 400 350 300 250 200 150 100 50 0 typical perfor a ce characteristics uw i cc shutdown vs v cc large-signal settling gain error vs v cc v cc (v) 2.5 3 3.5 4 4.5 5 5.5 gain error (%fsr) 2602 g07 0.4 0.3 0.2 0.1 0 0.1 ?.2 0.3 0.4 2.5 s/div v out 0.5v/div 2602 g09 v ref = v cc = 5v 1/4-scale to 3/4-scale (ltc2602/ltc2612/ltc2622) midscale glitch impulse power-on reset glitch headroom at rails vs output current i out (ma) 0 1 2 3 4 5 6 7 8 910 v out (v) 2602 g12 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 5v sourcing 3v sourcing 3v sinking 5v sinking multiplying frequency response supply current vs logic voltage exiting power-down to midscale frequency (hz) 1k db 0 ? ? ? ?2 ?5 ?8 ?1 ?4 ?7 ?0 ?3 ?6 1m 2602 g16 10k 100k v cc = 5v v ref (dc) = 2v v ref (ac) = 0.2v p-p code = full scale
8 ltc2602/ltc2612/ltc2622 2602fa 1v/div 0 ?0 10ma/div ?0 ?0 ?0 ?0 0 1 234 2602 g35 56 v cc = 5.5v v ref = 5.6v code = full scale v out swept v cc to 0v 1v/div 0 0 10ma/div 10 20 30 40 50 1 234 2602 g34 56 v cc = 5.5v v ref = 5.6v code = 0 v out swept 0v to v cc (ltc2602/ltc2612/ltc2622) typical perfor a ce characteristics uw output voltage noise, 0.1hz to 10hz short-circuit output current vs v out (sinking) short-circuit output current vs v out (sourcing) v out 10 v/div seconds 012345678910 2602 g17
9 ltc2602/ltc2612/ltc2622 2602fa pi n fu n ctio n s uuu cs/ld (pin 1): serial interface chip select/load input. when cs/ld is low, sck is enabled for shifting data on sdi into the register. when cs/ld is taken high, sck is dis- abled and the specified command (see table 1) is ex- ecuted. sck (pin 2): serial interface clock input. cmos and ttl compatible. sdi (pin 3): serial interface data input. data is applied to sdi for transfer to the device at the rising edge of sck. the block diagra w ltc2602/ltc2612/ltc2622 accept input word lengths of either 24 or 32 bits. ref (pin 4): reference voltage input. 0v v ref v cc . v out b and v out a (pins 5 and 8): dac analog voltage outputs. the output range is 0 ?v ref . v cc (pin 6): supply voltage input. 2.5v v cc 5.5v. gnd (pin 7): analog ground. v out a ref cs/ld sck v out b gnd v cc sdi 2602 bd 8 1 2 4 3 5 7 6 dac a dac b decode control logic 24-bit shift register dac register input register input register dac register figure 1 ti i g diagra u ww sdi cs/ld sck 2602 f01 t 2 t 10 t 5 t 7 t 6 t 1 t 3 t 4 1232324 c3 c2 c1 d1 d0
10 ltc2602/ltc2612/ltc2622 2602fa operatio u serial interface the cs/ld input is level triggered. when this input is taken low, it acts as a chip-select signal, activating the sdi and sck buffers and enabling the input shift register. data (sdi input) is transferred at the next 24 rising sck edges. the 4-bit command, c3-c0, is loaded first; then the 4-bit dac address, a3-a0; and finally the 16-bit data word. the data word comprises the 16-, 14- or 12-bit input code, ordered msb-to-lsb, followed by 0, 2 or 4 don?-care bits (ltc2602, ltc2612 and ltc2622 respectively). data can only be transferred to the device when the cs/ld signal is low.the rising edge of cs/ld ends the data transfer and causes the device to carry out the action specified in the 24-bit input word. the complete sequence is shown in figure 2a. the command (c3-c0) and address (a3-a0) assignments are shown in table 1. the first four commands in the table consist of write and update operations. a write operation loads a 16-bit data word from the 32-bit shift register into the input register of the selected dac, n. an update operation copies the data word from the input register to the dac register. once copied into the dac register, the data word becomes the active 16-, 14- or 12-bit input code, and is converted to an analog voltage at the dac output. the update operation also powers up the selected dac if it had been in power-down mode. the data path and registers are shown in the block diagram. while the minimum input word is 24 bits, it may optionally be extended to 32 bits to accommodate microprocessors which have a minimum word width of 16 bits (2 bytes). to use the 32-bit word width, 8 don?-care bits are transferred to the device first, followed by the 24-bit word as just described. figure 2b shows the 32-bit sequence. power-down mode for power-constrained applications, power-down mode can be used to reduce the supply current whenever less than two outputs are needed. when in power-down, the buffer amplifiers, bias circuits and reference inputs are disabled, and draw essentially zero current. the dac outputs are put into a high-impedance state, and the power-on reset the ltc2602/ltc2612/ltc2622 clear the outputs to zero scale when power is first applied, making system initializa- tion consistent and repeatable. for some applications, downstream circuits are active during dac power-up, and may be sensitive to nonzero outputs from the dac during this time. the ltc2602/ ltc2612/ltc2622 contain circuitry to reduce the power- on glitch; furthermore, the glitch amplitude can be made smaller by reducing the ramp rate of the power supply. for example, if the power supply is ramped to 5v in 1ms, the analog outputs rise less than 10mv above ground (typ) during power-on. see power-on reset glitch in the typi- cal performance characteristics section. power supply sequencing the voltage at ref (pin 4) should be kept within the range 0.3v v ref v cc + 0.3v (see absolute maximum ratings). particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at v cc (pin 6) is in transition. transfer function the digital-to-analog transfer function is v k v out ideal n ref () = ? ? ? ? ? ? 2 where k is the decimal equivalent of the binary dac input code, n is the resolution and v ref is the voltage at ref (pin 4). table 1. command* c3 c2 c1 c0 0000 w rite to input register n 0001 u pdate (power up) dac register n 0010 w rite to input register n, update (power up) all n 0011 w rite to and update (power up) n 0100 power down n 1111 no o peration address (n)* a3 a2 a1 a0 0000 dac a 0001 dac b 1111 all dacs *command and address codes not shown are reserved and should not be used.
11 ltc2602/ltc2612/ltc2622 2602fa c3 command address data (16 bits) c2 c1 c0 a3 a2 a1 a0 d13 d14 d15 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 2602 tbl01 msb lsb c3 command address data (14 bits + 2 don?-care bits) c2 c1 c0 a3 a2 a1 a0 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x 2602 tbl02 msb lsb c3 command address data (12 bits + 4 don?-care bits) c2 c1 c0 a3 a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x xx 2602 tbl03 msb lsb input word (ltc2602) input word (ltc2612) input word (ltc2622) operatio u output pins are passively pulled to ground through indi- vidual 90k ? resistors. input- and dac-register contents are not disturbed during power-down. either channel or both channels can be put into power- down mode by using command 0100 b in combination with the appropriate dac address, (n). the 16-bit data word is ignored. the supply and reference currents are reduced by approximately 50% for each dac powered down; the effective resistance at ref (pin 4) rises accordingly, becoming a high-impedance input (typically > 1g ? ) when both dacs are powered down. normal operation can be resumed by executing any com- mand which includes a dac update, as shown in table 1. the selected dac is powered up as its voltage output is updated. when a dac which is in a powered-down state is powered up and updated, normal settling is delayed. if one of the two dacs is in a powered-down state prior to the update command, the power-up delay is 5 s. if, on the other hand, both dacs are powered down, then the main bias generation circuit block has been automatically shut down in addition to the individual dac amplifiers and reference inputs. in this case, the power up delay time is 12 s (for v cc = 5v) or 30 s (for v cc = 3v). voltage outputs each of the two rail-to-rail amplifiers contained in these parts has guaranteed load regulation when sourcing or sinking up to 15ma at 5v (7.5ma at 3v). load regulation is a measure of the amplifier? ability to maintain the rated voltage accuracy over a wide range of load conditions. the measured change in output voltage per milliampere of forced load current change is ex- pressed in lsb/ma. dc output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from lsb/ma to ohms. the amplifiers?dc output impedance is 0.050 ? when driving a load well away from the rails. when drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 25 ? typical channel resistance of the output devices; e.g., when sinking 1ma, the minimum output voltage = 25 ? 1ma = 25mv. see the graph headroom at rails vs output current in the typical performance characteristics sec- tion. the amplifiers are stable driving capacitive loads of up to 1000pf.
12 ltc2602/ltc2612/ltc2622 2602fa operatio u board layout the excellent load regulation and dc crosstalk perfor- mance of these devices is achieved in part by keeping ?ignal?and ?ower?grounds separated internally and by reducing shared internal resistance. the gnd pin functions both as the node to which the reference and output voltages are referred and as a return path for power currents in the device. because of this, careful thought should be given to the grounding scheme and board layout in order to ensure rated performance. the pc board should have separate areas for the analog and digital sections of the circuit. this keeps digital signals away from sensitive analog signals and facilitates the use of separate digital and analog ground planes which have minimal capacitive and resistive interaction with each other. digital and analog ground planes should be joined at only one point, establishing a system star ground as close to the device? ground pin as possible. ideally, the analog ground plane should be located on the component side of the board, and should be allowed to run under the part to shield it from noise. analog ground should be a continu- ous and uninterrupted plane, except for necessary lead pads and vias, with signal traces on another layer. the gnd pin of the part should be connected to analog ground. resistance from the gnd pin to system star ground should be as low as possible. resistance here will add directly to the effective dc output impedance of the device (typically 0.050 ? ), and will degrade dc crosstalk. note that the ltc2602/ltc2612/ltc2622 are no more susceptible to these effects than other parts of their type; on the contrary, they allow layout-based performance improvements to shine rather than limiting attainable performance with excessive internal resistance. rail-to-rail output considerations in any rail-to-rail voltage output device, the output is limited to voltages within the supply range. since the analog outputs of the device cannot go below ground, they may limit for the lowest codes as shown in figure 3b. similarly, limiting can occur near full scale when the ref pin is tied to v cc . if v ref = v cc and the dac full-scale error (fse) is positive, the output for the highest codes limits at v cc as shown in figure 3c. no full-scale limiting can occur if v ref is less than v cc ?fse. offset and linearity are defined and tested over the region of the dac transfer function where no output limiting can occur.
13 ltc2602/ltc2612/ltc2622 2602fa operatio u 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 c2 c1 c0 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c3 x x x x x x x x cs/ld sck sdi command word address word data word don? care 2602 f02b figure 2a. ltc2602 24-bit load sequence (minimum input word) ltc2612 sdi data word 14-bit input code + 2 don? care bits ltc2622 sdi data word 12-bit input code + 4 don? care bits figure 2b. ltc2602 32-bit load sequence ltc2612 sdi data word 14-bit input code + 2 don? care bits ltc2622 sdi data word 12-bit input code + 4 don? care bits 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 c2 c1 c0 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c3 cs/ld sck sdi command word address word data word 24-bit input word yyyy f02a
14 ltc2602/ltc2612/ltc2622 2602fa operatio u figure 3. effects of rail-to-rail operation on a dac transfer curve. (a) overall transfer function (b) effect of negative offset for codes near zero scale (c) effect of positive full-scale error for codes near full scale 2600 f03 input code output voltage negative offset 0v 32,768 0 65,535 input code output voltage v ref = v cc v ref = v cc input code output voltage positive fse (b) (a) (c)
15 ltc2602/ltc2612/ltc2622 2602fa msop (ms8) 0603 0.53 0.152 (.021 .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.18 (.007) 0.254 (.010) 1.10 (.043) max 0.22 ?0.38 (.009 ?.015) typ 0.127 0.076 (.005 .003) 0.86 (.034) ref 0.65 (.0256) bsc 0 ?6 typ detail ? detail ? gauge plane 12 3 4 4.90 0.152 (.193 .006) 8 7 6 5 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) 0.52 (.0205) ref 5.23 (.206) min 3.20 ?3.45 (.126 ?.136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc ms8 package 8-lead plastic msop (reference ltc dwg # 05-08-1660) u package descriptio information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
16 ltc2602/ltc2612/ltc2622 2602fa part number description comments ltc1458/ltc1458l quad 12-bit rail-to-rail output dacs with added functionality ltc1458: v cc = 4.5v to 5.5v, v out = 0v to 4.096v ltc1458l: v cc = 2.7v to 5.5v, v out = 0v to 2.5v ltc1654 dual 14-bit rail-to-rail v out dac programmable speed/power, 3.5 s/750 a, 8 s/450 a ltc1655/ltc1655l single 16-bit v out dac with serial interface in so-8 v cc = 5v(3v), low power, deglitched ltc1657/ltc1657l parrallel 5v/3v 16-bit v out dac low power, deglitched, rail-to-rail v out ltc1660/ltc1665 octal 10/8-bit v out dac in 16-pin narrow ssop v cc = 2.7v to 5.5v, micropower, rail-to-rail output ltc1661 dual 10-bit v out dac in 8-lead msop package v cc = 2.7v to 5.5v, 60 a per dac, rail-to-rail output ltc1821 parallel 16-bit voltage output dac precision 16-bit settling in 2 s for 10v step ltc2600/ltc2610/ octal 16/14/12-bit rail-to-rail dacs in 16-lead ssop 250 a per dac, 2.5v to 5.5v supply range ltc2620 rail-to-rail output ? linear technology corporation 2003 rd/lt 1205 rev a ? printed in the usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com related parts

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